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Data Sheet
A m p l i fy t h e H u m a n E x p e r i e n c e
(R)
Comlinear CLC2600, CLC3600, CLC4600
Dual, Triple, and Quad 300MHz Amplifiers
features n 0.1dB gain flatness to 95MHz n 0.03%/0.04 differential gain/ phase error n 230MHz -3dB bandwidth at G = 2 n 300MHz -3dB bandwidth at G = 1 n 1,300V/s slew rate n 50mA output current n 3.3mA supply current n Fully specified at 5V supplies n CLC2600: Pb-free SOIC-8 n CLC4600: Pb-free SOIC-14 applications n Video line drivers n S-Video driver n Video switchers and routers n ADC buffer n Active filters n Cable drivers n Twisted pair driver/receiver
Comlinear CLC2600, CLC3600, CLC4600 Dual,Triple, and Quad 300MHz Amplifiers
General Description
The Comlinear CLC2600 (dual), CLC3600 (triple), and CLC4600 (quad) are high-performance, current feedback amplifiers. These amplifiers provide 300MHz unity gain bandwidth, 0.1dB gain flatness to 95MHz, and provide 1,300V/s slew rate exceeding the requirements of high-definition television (HDTV) and other multimedia applications. These Comlinear high-performance amplifiers also provide ample output current to drive multiple video loads. The Comlinear CLC2600, CLC3600, and CLC4600 are designed to operate from 5V supplies. They consume only 3.3mA of supply current per channel. The combination of high-speed, low-power, and excellent video performance make these amplifiers well suited for use in many general purpose, highspeed applications including standard definition and high definition video.
Typical Application - Driving Dual Video Loads
+Vs
75 Cable Input 75 Rf Rg 75 -Vs 75
75 Cable Output A 75
75 Cable Output B 75
Ordering Information
Part Number CLC2600ISO8X CLC2600ISO8 CLC3600ISO14X CLC3600ISO14 CLC4600ISO14X CLC4600ISO14 Package SOIC-8 SOIC-8 SOIC-14 SOIC-14 SOIC-14 SOIC-14 Pb-Free Yes Yes Yes Yes Yes Yes Operating Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C Packaging Method Reel Rail Reel Rail Reel Rail
Rev 1A
Moisture sensitivity level for all parts is MSL-1.
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Data Sheet
CLC2600 Pin Configuration
OUT1 -IN1 +IN1 -V S
1 2 3 4 8 7 6 5
CLC2600 Pin Assignments
Pin No. 1 2 3 4 5 6 7 8 Pin Name OUT1 -IN1 +IN1 -VS +IN2 -IN2 OUT2 +VS Description Output, channel 1 Negative input, channel 1 Positive input, channel 1 Negative supply Positive input, channel 2 Negative input, channel 2 Output, channel 2 Positive supply
+VS OUT2 -IN2 +IN2
Comlinear CLC2600, CLC3600, CLC4600 Dual, Triple, and Quad 300MHz Amplifiers
CLC3600 Pin Configuration
NC NC NC +VS +IN1 -IN1 OUT1
1 2 3 4 5 6 7 14 13 12 11 10 9 8
CLC3600 Pin Configuration
OUT2 -IN2 +IN2 -VS +IN3 -IN3 OUT3
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Pin Name NC NC NC +VS +IN1 -IN1 OUT1 OUT3 -IN3 +IN3 -VS +IN2 -IN2 OUT2
Description No Connect No Connect No Connect Positive supply Positive input, channel 1 Negative input, channel 1 Output, channel 1 Output, channel 3 Negative input, channel 3 Positive input, channel 3 Negative supply Positive input, channel 2 Negative input, channel 2 Output, channel 2
CLC4600 Pin Configuration
OUT1 -IN1 +IN1 +VS +IN2 -IN2 OUT2
1 2 3 4 5 6 7 14 13 12 11 10 9 8
CLC4600 Pin Configuration
OUT4 -IN4 +IN4 -VS +IN3 -IN3 OUT3
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Pin Name OUT1 -IN1 +IN1 +VS +IN2 -IN2 OUT2 OUT3 -IN3 +IN3 -VS +IN4 -IN4 OUT4
Description Output, channel 1 Negative input, channel 1 Positive input, channel 1 Positive supply Positive input, channel 2 Negative input, channel 2 Output, channel 2 Output, channel 3 Negative input, channel 3 Positive input, channel 3 Negative supply Positive input, channel 4 Negative input, channel 4 Output, channel 4
Rev 1A
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2
Data Sheet
Absolute Maximum Ratings
The safety of the device is not guaranteed when it is operated above the "Absolute Maximum Ratings". The device should not be operated at these "absolute" limits. Adhere to the "Recommended Operating Conditions" for proper device function. The information contained in the Electrical Characteristics tables and Typical Performance plots reflect the operating conditions noted on the tables and plots.
Comlinear CLC2600, CLC3600, CLC4600 Dual, Triple, and Quad 300MHz Amplifiers
Parameter Supply Voltage Input Voltage Range
Min 0 -Vs -0.5V
Max 7 or 14 +Vs +0.5V
Unit V V
Reliability Information
Parameter Junction Temperature Storage Temperature Range Lead Temperature (Soldering, 10s) Package Thermal Resistance 8-Lead SOIC 14-Lead SOIC
Notes: Package thermal resistance (qJA), JDEC standard, multi-layer test boards, still air.
Min -65
Typ
Max 150 150 260
Unit C C C C/W C/W
100 88
ESD Protection
Product Human Body Model (HBM) Charged Device Model (CDM) SOIC-8 2.5kV 2kV SOIC-14 2.5kV 2kV
Recommended Operating Conditions
Parameter Operating Temperature Range Supply Voltage Range Min -40 4 Typ Max +85 6 Unit C V
Rev 1A
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Data Sheet
Electrical Characteristics
TA = 25C, Vs = 5V, Rf = 510, RL = 100, G = 2; unless otherwise noted.
symbol
UGBW BWSS BWLS BW0.1dBSS BW0.1dBLS tR, tF tS OS SR HD2 HD3 THD DG DP en in+ inXTALK VIO dVIO Ibn dIbn Ibi dIbi PSRR AOL IS
parameter
-3dB Bandwidth -3dB Bandwidth Large Signal Bandwidth 0.1dB Gain Flatness 0.1dB Gain Flatness Rise and Fall Time Settling Time to 0.1% Overshoot Slew Rate 2nd Harmonic Distortion 3rd Harmonic Distortion Total Harmonic Distortion Differential Gain Differential Phase Input Voltage Noise Input Current Noise (+) Input Current Noise (-) Crosstalk Input Offset Voltage(1) Average Drift Input Bias Current Non-inverting(1) Average Drift Input Bias Current Inverting(1) Average Drift Power Supply Rejection Ratio(1) Open-Loop Transresistance Supply Current(1)
conditions
G = +1, VOUT = 0.2Vpp, Rf = 1.24k G = +2, VOUT = 0.2Vpp G = +2, VOUT = 4Vpp G = +2, VOUT = 0.2Vpp G = +2, VOUT = 4Vpp VOUT = 2V step; (10% to 90%) VOUT = 2V step VOUT = 0.2V step 4V step 2Vpp, 1MHz 2Vpp, 1MHz 2Vpp, 1MHz NTSC (3.58MHz), DC-coupled, RL = 150 NTSC (3.58MHz), DC-coupled, RL = 150 > 1MHz > 1MHz > 1MHz Channel-to-channel 5MHz
Min
typ
300 230 155 95 55 1.8 20 2.5 1300 -80 -86 -79.5 0.03 0.04 6.4 1.0 9.3 -56
Max
units
MHz
Frequency Domain Response
Comlinear CLC2600, CLC3600, CLC4600 Dual, Triple, and Quad 300MHz Amplifiers
MHz MHz MHz MHz ns ns % V/s dBc dBc dB % nV/Hz pA/Hz pA/Hz dB +8 3 18 mV V/C A nA/C A nA/C dB k
10 20 20 mA mA mA
Time Domain Response
Distortion/Noise Response
DC Performance
-8 -3 -18 DC VOUT = VS / 2
CLC2600 Total CLC3600 Total CLC4600 Total
1.4 15 1.3 2.6 4.4 16 65 580
6.6 13.2 13.2
60
Input Characteristics
RIN CIN CMIR CMRR RO VOUT IOUT ISC
notes: 1. 100% tested at 25C
Input Resistance Input Capacitance Common Mode Input Range Common Mode Rejection Ratio(1) Output Resistance Output Voltage Swing Output Current Short-Circuit Output Current
Non-inverting
19 1 2.3
M pF V dB m 2.6 V V mA mA
DC Closed Loop, DC RL = 100 (1) RL = 1k VOUT = VS / 2
52
57 110
Output Characteristics
-2.6 3 3.3 50 67
Rev 1A
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Data Sheet
Typical Performance Characteristics
TA = 25C, Vs = 5V, Rf = 510, RL = 100, G = 2; unless otherwise noted. Non-Inverting Frequency Response
1 0
Inverting Frequency Response
1
Comlinear CLC2600, CLC3600, CLC4600 Dual, Triple, and Quad 300MHz Amplifiers
0
Normalized Gain (dB)
Normalized Gain (dB)
-1 -2
-1 -2
G = 10 G=5
G = -10 G = -5
-3 -4 G=2 -5 -6 -7 0.1 1 10 100 1000 VOUT = 0.2Vpp G=1 Rf = 1.24k
-3 -4 -5 -6 -7 0.1 1 10 100 1000 VOUT = 0.2Vpp
G = -2
G = -1
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. CL
1 0
Frequency Response vs. RL
2 RL = 5K 1 RL = 1K
Normalized Gain (dB)
-2 -3 -4 -5 -6 -7 0.1 1 VOUT = 0.2Vpp
CL = 500pF Rs = 9 CL = 100pF Rs = 20 CL = 50pF Rs = 30 CL = 10pF Rs = 40 10 100 1000
Normalized Gain (dB)
-1
CL = 1000pF Rs = 5
0 -1 -2 -3 -4 -5 -6 0.1 1 10 100 1000 VOUT = 0.2Vpp RL = 150 RL = 50
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. VOUT
1 0
Frequency Response vs. Temperature
1 0
Normalized Gain (dB)
-2 -3 -4 -5 -6 -7 0.1 1
VOUT = 4Vpp
Normalized Gain (dB)
-1
-1 -2 -3 -4 -5 -6 -7 + 85degC VOUT = 2Vpp + 25degC
VOUT = 2Vpp
- 40degC
VOUT = 1Vpp
Rev 1A
10
100
1000
0.1
1
10
100
1000
Frequency (MHz)
Frequency (MHz)
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Data Sheet
Typical Performance Characteristics - Continued
TA = 25C, Vs = 5V, Rf = 510, RL = 100, G = 2; unless otherwise noted. Frequency Response vs. Rf at G=1
3 2 Rf = 510 Rf = 750 Rf = 1k 0 -1 -2 -3 -4 0.1 1 10 100 1000 Rf = 1.24k Rf = 1.5k
Frequency Response vs. Rf at G=2
1 0 Rf = 250
Comlinear CLC2600, CLC3600, CLC4600 Dual, Triple, and Quad 300MHz Amplifiers
Normalized Gain (dB)
1
Normalized Gain (dB)
-1 -2 -3 -4 -5 -6 -7 0.1 1 10 100 1000 Rf = 1.5k G=2 Rf = 510
Rf = 1k
G=1
Frequency (MHz)
Frequency (MHz)
Frequency Response vs. Rf at G=5
1 0
Gain Flatness
0.1 0
Normalized Gain (dB)
Rf = 510 Rf = 100 Rf = 200
Normalized Gain (dB)
-1 -2 -3 -4 -5 -6 -7 0.1 1 G=5
-0.1 -0.2 -0.3 -0.4 -0.5
VOUT = 2Vpp
10
100
1000
0.1
1
10
100
1000
Frequency (MHz)
Frequency (MHz)
Open Loop Transimpendance Gain/Phase vs. Frequency
1M 0 -20 100k 10k 1k 100 10
Gain Phase
Input Voltage Noise
13 12 11
Transimpedance Phase (deg)
Transimpedance Gain ()
-40 -60 -80 -100 -120 -140 -160 -180 10k 100k 1M 10M 100M 1G -200
Noise (nV/Hz)
10 9 8 7 6 5 4 0.0001 0.001 0.01 0.1 1 10 100
Rev 1A
Frequency (Hz)
Frequency (MHz)
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Data Sheet
Typical Performance Characteristics - Continued
TA = 25C, Vs = 5V, Rf = 510, RL = 100, G = 2; unless otherwise noted. 2nd Harmonic Distortion vs. RL
-55 -60 RL = 100 -65 -60
3rd Harmonic Distortion vs. RL
-50
Comlinear CLC2600, CLC3600, CLC4600 Dual, Triple, and Quad 300MHz Amplifiers
-55
Distortion (dBc)
-70 -75 -80 -85 -90 -95 0 5 10 15 20 VOUT = 2Vpp RL = 1k
Distortion (dBc)
-65 -70 -75
RL = 100
RL = 1k -80 -85 -90 0 5 10 15 20
VOUT = 2Vpp
Frequency (MHz)
Frequency (MHz)
2nd Harmonic Distortion vs. VOUT
-55 -60 20MHz -65
3rd Harmonic Distortion vs. VOUT
-45 -50 -55 20MHz
Distortion (dBc)
-70 -75 5MHz -80 -85 1MHz -90 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5
Distortion (dBc)
-60 -65 -70 -75 -80 -85 -90 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 1MHz 5MHz
Output Amplitude (Vpp)
Output Amplitude (Vpp)
CMRR vs. Frequency
0 -10
PSRR vs. Frequency
-20 -30
CMRR (dB)
-30 -40 -50 -60
PSRR (dB)
-20
-40 -50 -60 -70 -80
Rev 1A
10
100
1k
10k
100k
1M
10M 100M
10
100
1k
10k
100k
1M
10M 100M
Frequency (Hz)
Frequency (Hz)
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Data Sheet
Typical Performance Characteristics - Continued
TA = 25C, Vs = 5V, Rf = 510, RL = 100, G = 2; unless otherwise noted. Small Signal Pulse Response
0.125 0.1 0.075 0.05
Large Signal Pulse Response
2.5
Comlinear CLC2600, CLC3600, CLC4600 Dual, Triple, and Quad 300MHz Amplifiers
2.0 1.5 1.0
Voltage (V)
0 -0.025 -0.05 -0.075 -0.1 -0.125 0 20 40 60 80 100 120 140 160 180 200
Voltage (V)
0.025
0.5 0.0 -0.5 -1.0 -1.5 -2.0 -2.5 0 20 40 60 80 100 120 140 160 180 200
Time (ns)
Time (ns)
Crosstalk vs. Frequency
-30 -35 -45 -50 -40
Closed Loop Output Impedance vs. Frequency
10
-55 -60 -65 -70 -75 -80 -85 -90 -95 0.1 1 10 100 VOUT = 2Vpp
Output Impedance ()
Crosstalk (dB)
1
0.1
Frequency (MHz)
10k
100k
1M
10M
100M
Frequency (Hz)
Differential Gain & Phase AC Coupled
0.04 0.03 RL = 150 AC coupled into 220F
Differential Gain & Phase DC Coupled
0.04 0.03 RL = 150 DC coupled
Diff Gain (%) / Diff Phase ()
Diff Gain (%) / Diff Phase ()
0.02 0.01 DG 0 -0.01 -0.02 -0.03 -0.04 -0.7 -0.5 -0.3 -0.1 0.1 Input Voltage (V) 0.3 0.5 0.7 DP
0.02 0.01 0 -0.01 -0.02 -0.03 -0.04 -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 0.7 DG
DP
Rev 1A
Input Voltage (V)
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8
Data Sheet
General Information - Current Feedback Technology
Advantages of CFB Technology The CLCx600 Family of amplifiers utilize current feedback (CFB) technology to achieve superior performance. The primary advantage of CFB technology is higher slew rate performance when compared to voltage feedback (VFB) architecture. High slew rate contributes directly to better large signal pulse response, full power bandwidth, and distortion. CFB also alleviates the traditional trade-off between closed loop gain and usable bandwidth that is seen with a VFB amplifier. With CFB, the bandwidth is primarily determined by the value of the feedback resistor, Rf. By using optimum feedback resistor values, the bandwidth of a CFB amplifier remains nearly constant with different gain configurations. When designing with CFB amplifiers always abide by these basic rules: * Use the recommended feedback resistor value * Do not use reactive (capacitors, diodes, inductors, etc.) elements in the direct feedback path * Avoid stray or parasitic capacitance across feedback resistors * Follow general high-speed amplifier layout guidelines * Ensure proper precautions have been made for driving capacitive loads
Ierr
x1
Zo*Ierr Rf
VOUT
Comlinear CLC2600, CLC3600, CLC4600 Dual, Triple, and Quad 300MHz Amplifiers
VIN
Rg
RL
VOUT VIN
=-
Rf Rg
+ 1+
1 Rf Zo(j)
Eq. 2
Figure 2. Inverting Gain Configuration with First Order Transfer Function CFB Technology - Theory of Operation Figure 1 shows a simple representation of a current feedback amplifier that is configured in the traditional noninverting gain configuration. Instead of having two high-impedance inputs similar to a VFB amplifier, the inputs of a CFB amplifier are connected across a unity gain buffer. This buffer has a high impedance input and a low impedance output. It can source or sink current (Ierr) as needed to force the non-inverting input to track the value of Vin. The CFB architecture employs a high gain trans-impedance stage that senses Ierr and drives the output to a value of (Zo(j) * Ierr) volts. With the application of negative feedback, the amplifier will drive the output to a voltage in a manner which tries to drive Ierr to zero. In practice, primarily due to limitations on the value of Zo(j), Ierr remains a small but finite value. A closer look at the closed loop transfer function (Eq.1) shows the effect of the trans-impedance, Zo(j) on the gain of the circuit. At low frequencies where Zo(j) is very large with respect to Rf, the second term of the equation approaches unity, allowing Rf and Rg to set the gain. At higher frequencies, the value of Zo(j) will roll off, and the effect of the secondary term will begin to dominate. The -3dB small signal parameter specifies the frequency where the value Zo(j) equals the value of Rf causing the gain to drop by 0.707 of the value at DC. For more information regarding current feedback amplifiers, visit www.cadeka.com for detailed application notes, such as AN-3: The Ins and Outs of Current Feedback Amplifiers.
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VIN
Ierr
x1
Zo*Ierr Rf
VOUT
RL
Rg
VOUT VIN
= 1+
Rf Rg
+ 1+
1 Rf Zo(j)
Rev 1A
Eq. 1
Figure 1. Non-Inverting Gain Configuration with First Order Transfer Function
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Data Sheet
Application Information
Basic Operation Figures 3, 4, and 5 illustrate typical circuit configurations for non-inverting, inverting, and unity gain topologies for dual supply applications. They show the recommended bypass capacitor values and overall closed loop gain equations.
+Vs 6.8F
CFB amplifiers can be used in unity gain configurations. Do not use the traditional voltage follower circuit, where the output is tied directly to the inverting input. With a CFB amplifier, a feedback resistor of appropriate value must be used to prevent unstable behavior. Refer to figure 5 and Table 1. Although this seems cumbersome, it does allow a degree of freedom to adjust the passband characteristics. Feedback Resistor Selection One of the key design considerations when using a CFB amplifier is the selection of the feedback resistor, Rf. Rf is used in conjunction with Rg to set the gain in the traditional non-inverting and inverting circuit configurations. Refer to figures 3 and 4. As discussed in the Current Feedback Technology section, the value of the feedback resistor has a pronounced effect on the frequency response of the circuit. Table 1, provides recommended Rf and associated Rg values for various gain settings. These values produce the optimum frequency response, maximum bandwidth with minimum peaking. Adjust these values to optimize performance for a specific application. The typical performance characteristics section includes plots that illustrate how the bandwidth is directly affected by the value of Rf at various gain settings.
Comlinear CLC2600, CLC3600, CLC4600 Dual, Triple, and Quad 300MHz Amplifiers
Input
+ -
0.1F Output 0.1F RL Rf
G = 1 + (Rf/Rg)
Rg -Vs
6.8F
Figure 3. Typical Non-Inverting Gain Circuit
+Vs
6.8F
R1 Input Rg
+ -
0.1F Output 0.1F 6.8F -Vs RL Rf
G = - (Rf/Rg) For optimum input offset voltage set R1 = Rf || Rg
Gain (V/V 1 2 5
Rf () 1240 510 200
Rg () 510 50
0.1dB BW (MHz) 129 140 18
-3dB BW (MHz) 300 230 111
Figure 4. Typical Inverting Gain Circuit
Table 1: Recommended Rf vs. Gain
+Vs
6.8F
Input
+ -
0.1F Output 0.1F 6.8F -Vs RL Rf
G=1 Rf is required for CFB amplifiers
In general, lowering the value of Rf from the recommended value will extend the bandwidth at the expense of additional high frequency gain peaking. This will cause increased overshoot and ringing in the pulse response characteristics. Reducing Rf too much will eventually cause oscillatory behavior. Increasing the value of Rf will lower the bandwidth. Lowering the bandwidth creates a flatter frequency response and improves 0.1dB bandwidth performance. This is important in applications such as video. Further increase in Rf will cause premature gain rolloff and adversely affect gain flatness.
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Rev 1A
Figure 5. Typical Unity Gain (G=1) Circuit
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Data Sheet
Driving Capacitive Loads Increased phase delay at the output due to capacitive loading can cause ringing, peaking in the frequency response, and possible unstable behavior. Use a series resistance, RS, between the amplifier and the load to help improve stability and settling performance. Refer to Figure 6.
ringing. Refer to the layout considerations section for additional information regarding high speed layout techniques. Overdrive Recovery An overdrive condition is defined as the point when either one of the inputs or the output exceed their specified voltage range. Overdrive recovery is the time needed for the amplifier to return to its normal or linear operating point. The recovery time varies, based on whether the input or output is overdriven and by how much the range is exceeded. The CLCx600 Family will typically recover in less than 10ns from an overdrive condition. Figure 7 shows the CLC2600 in an overdriven condition.
1.00 0.75 0.50 Input Output 0.00 -0.25 -0.50 -0.75 -1.00 0 20 40 60 80 100 120 140 160 180 200 0 -1 -2 -3 -4 4 3 2
Comlinear CLC2600, CLC3600, CLC4600 Dual, Triple, and Quad 300MHz Amplifiers
Input
+ Rf Rg
Rs CL RL
Output
Figure 6. Addition of RS for Driving Capacitive Loads Table 2 provides the recommended RS for various capacitive loads. The recommended RS values result in <=0.5dB peaking in the frequency response. The Frequency Response vs. CL plot, on page 5, illustrates the response of the CLCx600 Family.
CL (pF) 10 50 100 RS () 40 30 20 -3dB BW (MHz) 265 140 105
VIN = 1.5Vpp G=5
Output Voltage (V)
Input Voltage (V)
0.25
1
Time (ns)
Figure 7. Overdrive Recovery Table 1: Recommended RS vs. CL For a given load capacitance, adjust RS to optimize the tradeoff between settling time and bandwidth. In general, reducing RS will increase bandwidth at the expense of additional overshoot and ringing. Parasitic Capacitance on the Inverting Input Physical connections between components create unintentional or parasitic resistive, capacitive, and inductive elements. Parasitic capacitance at the inverting input can be especially troublesome with high frequency amplifiers. A parasitic capacitance on this node will be in parallel with the gain setting resistor Rg. At high frequencies, its impedance can begin to raise the system gain by making Rg appear smaller. In general, avoid adding any additional parasitic capacitance at this node. In addition, stray capacitance across the Rf resistor can induce peaking and high frequency
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Power Dissipation For most applications, the power dissipation due to driving external loads should be low enough to ensure a safe operating condition. However, applications with low impedance, DC coupled loads should be analyzed to ensure that maximum allowed junction temperature is not exceeded. Guidelines listed below can be used to verify that the particular application will not cause the device to operate beyond it's intended operating range. Maximum power levels are set by the absolute maximum junction rating of 150C. To calculate the junction temperature, the package thermal resistance value ThetaJA (JA) is used along with the total die power dissipation.
Rev 1A
TJunction = TAmbient + (JA x PD)
Where TAmbient is the temperature of the working environment.
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Data Sheet
Maximum Power Dissipation (W)
In order to determine PD, the power dissipated in the load needs to be subtracted from the total power delivered by the supplies. PD = Psupply - Pload Supply power is calculated by the standard power equation. Psupply = Vsupply x IRMS supply Vsupply = VS+ - VSPower delivered to a purely resistive load is: Pload = ((VLOAD)RMS2)/Rloadeff The effective load resistor (Rloadeff) will need to include the effect of the feedback network. For instance, Rloadeff in figure 3 would be calculated as: RL || (Rf + Rg) These measurements are basic and are relatively easy to perform with standard lab equipment. For design purposes however, prior knowledge of actual signal levels and load impedance is needed to determine the dissipated power. Here, PD can be found from PD = PQuiescent + PDynamic - PLoad Quiescent power can be derived from the specified IS values along with known supply voltage, VSupply. Load power can be calculated as above with the desired signal amplitudes using: (VLOAD)RMS = VPEAK / 2 ( ILOAD)RMS = ( VLOAD)RMS / Rloadeff The dynamic power is focused primarily within the output stage driving the load. This value can be calculated as: PDYNAMIC = (VS+ - VLOAD)RMS x ( ILOAD)RMS Assuming the load is referenced in the middle of the power rails or Vsupply/2. Figure 8 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 8 and 14 lead SOIC packages.
2.5
2
SOIC-14
1.5
Comlinear CLC2600, CLC3600, CLC4600 Dual, Triple, and Quad 300MHz Amplifiers
1
SOIC-8
0.5
0 -40 -20 0 20 40 60 80
Ambient Temperature (C)
Figure 8. Maximum Power Derating
Better thermal ratings can be achieved by maximizing PC board metallization at the package pins. However, be careful of stray capacitance on the input pins. In addition, increased airflow across the package can also help to reduce the effective JA of the package. In the event the outputs are momentarily shorted to a low impedance path, internal circuitry and output metallization are set to limit and handle up to 65mA of output current. However, extended duration under these conditions may not guarantee that the maximum junction temperature (+150C) is not exceeded. Layout Considerations General layout and supply bypassing play major roles in high frequency performance. CADEKA has evaluation boards to use as a guide for high frequency layout and as aid in device testing and characterization. Follow the steps below as a basis for high frequency layout: * Include 6.8F and 0.1F ceramic capacitors for power supply decoupling * Place the 6.8F capacitor within 0.75 inches of the power pin * Place the 0.1F capacitor within 0.1 inches of the power pin * Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance * Minimize all trace lengths to reduce series inductances Refer to the evaluation board layouts below for more information.
Rev 1A
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Data Sheet
Evaluation Board Information The following evaluation boards are available to aid in the testing and layout of these devices: Evaluation Board # CEB006 CEB018 Products CLC2600 CLC3600, CLC4600
Comlinear CLC2600, CLC3600, CLC4600 Dual, Triple, and Quad 300MHz Amplifiers
Evaluation Board Schematics Evaluation board schematics and layouts are shown in Figures 9-14. These evaluation boards are built for dual- supply operation. Follow these steps to use the board in a single-supply application: 1. Short -Vs to ground. 2. Use C3 and C4, if the -VS pin of the amplifier is not directly connected to the ground plane.
Figure 10. CEB006 Top View
Figure 11. CEB006 Bottom View
Figure 9. CEB006 Schematic
Rev 1A
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Data Sheet
Comlinear CLC2600, CLC3600, CLC4600 Dual, Triple, and Quad 300MHz Amplifiers
Figure 14. CEB018 Bottom View
Figure 12. CEB018 Schematic
Figure 13. CEB018 Top View
Rev 1A
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14
Data Sheet
Mechanical Dimensions
SOIC-8 Package
Comlinear CLC2600, CLC3600, CLC4600 Dual, Triple, and Quad 300MHz Amplifiers
SOIC-14 Package
Rev 1A
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CADEKA, the CADEKA logo design, and Comlinear and the Comlinear logo design, are trademarks or registered trademarks of CADEKA Microcircuits LLC. All other brand and product names may be trademarks of their respective companies. CADEKA reserves the right to make changes to any products and services herein at any time without notice. CADEKA does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright (c)2008 by CADEKA Microcircuits LLC. All rights reserved.
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